1. Field of the Invention
The present invention relates to a thin-film magnetic memory device, and more specifically, it relates to a random-access thin-film magnetic memory device comprising memory cells each having a magnetic tunnel junction (MTJ).
2. Description of the Background Art
A MRAM (magnetic random access memory) device has recently been watched with interest as an advanced nonvolatile semiconductor memory device. The MRAM device is a nonvolatile memory device storing data in a plurality of thin-film magnetic materials formed on a semiconductor integrated circuit in a nonvolatile manner, with each thin-film magnetic body accessible at random. In particular, it has recently been announced that the performance of the MRAM device remarkably progresses when employing thin-film magnetic bodies utilizing magnetic tunnel junctions (MTJ) as memory cells. Technical literature such as xe2x80x9cA 10ns Read and Write Non-Volatile Memory Array using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000 discloses such an MRAM device comprising memory cells having magnetic tunnel junctions.
A memory cell (hereinafter referred to also as xe2x80x9cMTJ memory cellxe2x80x9d) having a magnetic tunnel junction, formable with an MTJ element and an access element such as a transistor, for example, is advantageous also for high integration. The MTJ element has a magnetic layer magnetizable in a direction responsive to an applied magnetic field, and the MTJ memory cell stores data through such a characteristic that the electric resistance (junction resistance) in the MTJ element varies with the direction of magnetization of the magnetic layer.
In order to read the data stored in the MTJ memory cell, electric resistance difference responsive to the level of the stored data must be detected. More specifically, the data is read on the basis of a current, varying with the electric resistance (i.e., the stored data), passing through the MTJ memory cell. In general, the MTJ element has electric resistance of several 10 kxcexa9, with electric resistance difference of about 20 to 30% resulting from difference between the levels of stored data. In consideration of the reliability of the MTJ element, a voltage of about 0.5 V is properly applied in data reading and hence the aforementioned pass current remains on the order of microamperes (xcexcA: 10xe2x88x926 A).
On the other hand, a large capacity memory array generally includes a plurality of bit lines provided in correspondence to rows or columns and a data line, provided in common in correspondence to the plurality of bit lines, connected to a circuit detecting stored data. In this structure, the data line and a selected bit line are charged to a prescribed voltage level for supplying a pass current to a memory cell in data reading, while the data line is electrically coupled not only to the selected bit line but also to the remaining non-selected bit lines through transistors or the like. Thus, unignorable parasitic capacitance of the transistors or the like is applied to the data line.
This parasitic capacitance applied to the data line inhibits the charge of the data line etc. to the prescribed level, leading to hindrance to high-speed data reading.
In the aforementioned structure, further, a circuit is generally provided every bit line for supplying a data write current responsive to write data to the selected bit line in data writing, while a signal line or the like is arranged in common in correspondence to this circuit for transmitting the write data.
Also in this structure, the signal line or the like arranged in common is electrically coupled not only to a selected circuit but also to non-selected circuits. Consequently, unignorable parasitic capacitance of the non-selected circuits is applied to the signal line or the like. The parasitic capacitance applied to the signal line or the like results in propagation delay of the write data in data writing, to hinder high-speed data writing.
The present invention has been proposed in order to solve the aforementioned problems, and an object thereof is to provide a structure of a thin-film magnetic memory device capable of executing high-speed data reading and high-speed data writing by suppressing parasitic capacitance applied to a data line and a signal line or the like. transmitting write data or the like.
The thin-film magnetic memory device according to the present invention includes a plurality of memory cells arranged in rows and columns, a plurality of first bit lines, X write data lines transmitting write data and a plurality of first write control circuits. The plurality of memory cells magnetically store data. The plurality of first bit lines are provided corresponding to the memory cell columns respectively. The plurality of first bit lines are divided into a plurality of groups. Each of the plurality of groups includes X (X: integer of at least two) first bit lines. The plurality of first write control circuits are provided corresponding to the plurality of first bit lines respectively for supplying a data write current in accordance with the write data. The X write data lines are electrically coupled with corresponding X first write control circuits respectively in each of groups, respectively.
In this thin-film magnetic memory device, the plurality of first bit lines are divided into a plurality of groups each including X first bit lines. The X write data lines are provided for transmitting the write data. Each of the X write data lines is electrically coupled with X first write control circuits belonging to each group. According to the present invention, the write control circuits electrically connected with the X write data lines are uniformly divided as hereinabove described, so that parasitic capacitance applied to the write data lines following electrical connection with the write control circuits can be suppressed. Thus, the propagation time for the write data transmitted through the write data lines can be reduced for executing high-speed data writing.
Alternatively, the thin-film magnetic memory device according to the present invention includes a plurality of memory cells arranged in rows and columns, a plurality of first bit lines, Y read data lines, Y read circuits, a plurality of column selection lines and Y connection control parts. The plurality of memory cells magnetically store data. The plurality of first bit lines are provided corresponding to the memory cell columns respectively. The plurality of first bit lines are divided into a plurality of first groups in data reading. Each of the plurality of first groups includes Y (Y: integer of at least two) first bit lines. At least one of the Y read data lines is supplied with a current in a state electrically connected with a selected memory cell among the plurality of memory cells selected as a subject for data read coupled to a first voltage in data reading. The Y read circuits are provided corresponding to the Y read data lines so that each read circuit electrically couples the corresponding read data line and a second voltage with each other in data reading. The Y read circuits generate read data on the basis of currents passing through the corresponding read data lines. The plurality of column selection lines are provided corresponding to the plurality of first groups respectively. A plurality of connection control parts are provided corresponding to the plurality of first groups respectively so that each connection control part electrically couples the corresponding Y first bit lines and the Y read data lines, respectively, in the corresponding first group among the plurality of first groups in response to activation of the corresponding column selection line.
In this thin-film magnetic memory device, the plurality of first bit lines are divided into the plurality of first groups each including Y first bit lines. The Y read data lines are provided so that a data read current passes therethrough in data reading. The Y connection control parts are provided for electrically coupling the Y first bit lines and the Y read data lines with each other every first group. According to the present invention, therefore, the connection control parts electrically connected with the Y read data lines are uniformly divided so that parasitic capacitance applied to the read data lines following electrical connection with the connection control parts can be suppressed. Thus, a time for charging the read data lines to a prescribed voltage level can be reduced for executing high-speed data reading.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.